The present disclosure relates to a delayed locked loop (DLL) circuit, and more particularly to a delayed locked loop (DLL) for guaranteeing an initial delay period of a delay line, thereby preventing a locking fail from being generated.
With the increasing degree of integration of a semiconductor memory, the semiconductor memory has been continuously improved to enhance its operation speed. In order to enhance the operation speed of the semiconductor memory, a synchronous memory device capable of being synchronized with a clock signal received from an external part of a memory chip has been recently introduced to the market.
However, if the above-mentioned synchronous memory synchronizes its data with the external clock signal, and outputs the synchronized result, an unexpected delay of “tAC” (output data Access time from Clk) occurs, and the number of valid data windows is reduced, such that an unexpected faulty operation occurs in the synchronous memory which is operating at high frequency. Therefore, in order to allow data to be correctly synchronized with a rising edge or a falling edge of the clock signal, a DLL circuit has been recently developed. The DLL circuit generates a DLL clock signal capable of delaying the external clock signal by a predetermined period denoted by “tCK-tAC”, such that the data can be correctly synchronized with the rising- or falling-edge of the clock signal.
The above-mentioned DLL circuit generates an internal clock signal for compensating for internal delay elements of a DRAM by an external clock signal, and this operation of the DDL circuit is generally called a locking state.
The above-mentioned locking state indicates that a reference clock signal (refclk) and a feedback clock signal (fbclk) are synchronized with each other. The conventional DLL adjusts an initial delay period of an initial delay line, and synchronizes the feedback clock signal (fbclk) with the reference clock signal (refclk).
FIGS. 1A and 1B show timing diagrams of the reference clock signal (refclk) and the feedback clock signal (fbclk) of the conventional DLL.
Referring to FIG. 1A, provided that the feedback clock signal (fbclk) enters the (a) state when the initial delay period of the delay line is set to “0”, and the initial delay period of the delay line is set to “X”, the feedback clock signal (fbclk) enters the (b) state, such that the feedback clock signal (fbclk) is synchronized with the reference clock signal (refclk).
Under this locking state, if an operation voltage of the DLL drops, the feedback clock signal (fbclk) is delayed by a predetermined period (Y), such that it enters the (c) state. As a result, the DLL enters a specific state in which the reference clock signal (refclk) is not synchronized with the feedback clock signal (fbclk). In this case, the specific state is generally called a locking fail state. Under this situation, the DLL adjusts the initial delay period of the delay line, and synchronizes the reference clock signal (refclk) with the feedback clock signal (fbclk), such that it recovers the locking state.
For example, if the feedback clock signal (fbclk) is delayed by a predetermined delay period “Y” due to the drop of the operation voltage, and the initial delay period of the delay line is reduced to a specific value “X-Y”, the delay period “Y” increased by the drop of the operation voltage and the other delay period “Y” decreased from the initial delay period are compensated for, the feedback clock (fbclk) enters the (b) state, such that the DLL recovers the locking state.
However, as can be seen from FIG. 1B, if the initial delay period “X” of the delay line is less than the delay period “Y” during which the feedback clock signal (fbclk) is delayed due to the drop of the operation voltage, the initial delay period of the delay line is reduced, such that the DLL cannot recover the locking state.
The above-mentioned problems can be solved by establishing a large-sized initial delay period of the delay line. However, the initial delay period is unnecessarily set to the large-sized delay period even when the initial delay period of the delay line is sufficiently guaranteed, such that it is very vulnerable to power noise.